1. Field of the Invention
The present invention relates to an AD conversion circuit and a solid-state imaging apparatus including the AD conversion circuit.
Priority is claimed on Japanese Patent Application No. 2012-206292, filed Sep. 19, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
As an example of a solid-state imaging apparatus using a time-to-digital converter (TDC) type AD conversion circuit, a constitution described in Japanese Unexamined Patent Application, First Publication No. 2008-92091 and Japanese Unexamined Patent Application, First Publication No. 2009-38726 is known. FIG. 9 illustrates a part taken from a constitution of the TDC type AD conversion circuit when an oscillation circuit referred to as a so-called “asymmetric type oscillation circuit” is used as a voltage controlled oscillator (VCO) of an AD conversion circuit. First, the constitution and operation of the circuit of FIG. 9 will be described.
The circuit illustrated in FIG. 9 includes a VCO 1100, a latch unit 1108, a counter 1105, a detection circuit 1107, and an encoding circuit 1106. The VCO 1100 includes an oscillation circuit in which seventeen delay units (NAND circuits NAND[0] to NAND[16]) are connected in a ring shape. The latch unit 1108 latches an output signal (lower phase signals CK[0] to CK[15]) of the VCO 1100. The counter 1105 has a counter circuit which counts a lower phase signal CK[13] from the NAND circuit NAND[13] output through the latch unit 1108 as a count clock. The counter 1105 counts a rising edge of the lower phase signal CK[13]. The detection circuit 1107 detects a predetermined logic state based on the lower phase signals CK[0] to CK[15] latched by the latch unit 1108. The encoding circuit 1106 encodes the logic state detected by the detection circuit 1107 into a binary number.
A start pulse StartP is input to one input terminal of the NAND circuit NAND[0] constituting the VCO 1100 and an output signal of the NAND circuit NAND[16] is input to the other input terminal thereof. A power supply voltage VDD is input to one input terminal of the NAND circuits NAND[1] to NAND[15] and an output signal of the NAND circuit of a preceding stage is input to the other input terminal thereof. The power supply voltage VDD is set to be a high level during an operation period of the AD conversion circuit. An output signal of the NAND circuit NAND[13] is input to one input terminal of the NAND circuit NAND[16] and an output signal of the NAND circuit NAND[15] of a preceding stage is input to the other input terminal thereof. An output signal of the NAND circuit NAND[13] is input to the NAND circuit NAND[16] three stages later, in addition to the NAND circuit NAND[14] one stage later.
A signal based on the start pulse StartP input to the NAND circuit NAND[0] is transmitted through two types of paths and passes through the NAND circuits NAND[0] to NAND[16]. A first path is a path to which a signal is transmitted through a signal line which connects the other input terminal of each NAND circuit with an output terminal of the NAND circuit of the preceding stage thereof. A second path is a path (a bypass path) to which a signal output from the NAND circuit NAND[13] is transmitted through a signal line which connects the output terminal of the NAND circuit NAND[13] with an input terminal of the NAND circuit NAND[16]. The signal transmitted through the second path reaches the NAND circuit NAND [16] by bypassing these NAND circuits NAND[14] and NAND[15], without passing through the NAND circuits NAND[14] and NAND[15] on the first path. By the above constitution, a feed forward loop is formed and thus the so-called ‘asymmetric type oscillation circuit” is constituted.
Next, an operation of the circuit illustrated in FIG. 9 will be described. FIG. 10 illustrates waveforms of the start pulse StartP and the output signal (lower phase signals CK[0] to CK[16]) of the VCO 1100. First, a logic state of the start pulse StartP is changed from an L (low) state to an H (high) state, such that the VCO 1100 starts a transition operation. In the transition operation, the logic states of the signals output from each of the NAND circuits constituting the VCO 1100 are changed in order. The VCO 1100 starts the transition operation and simultaneously, the counter 1105 starts a count and a reference signal generation unit (not illustrated) starts to generate a ramp wave (a reference signal). The ramp wave generated by the reference signal generation unit is a signal of which the level increases or decreases in one direction as time passes.
An analog signal and the ramp wave which are targets of the AD conversion are input to a comparison unit (not illustrated). At the same time, the lower phase signals CK[0] to CK[15] are input to the latch unit 1108 and the lower phase signal CK[13] is input to the counter 1105 through the latch unit 1108. When a large and small relationship between the two input signals input to the comparison unit is replaced, a comparison output CO of the comparison unit is inverted. At this time, the latch unit 1108 latches the logic state corresponding to the lower phase signals CK[0] to CK[15] and the counter 1105 latches a count value (an upper count value). The lower phase signal latched by the latch unit 1108 is encoded (binarized) by the detection circuit 1107 and the encoding circuit 1106 and thus becomes lower data of digital data, and the upper count value latched by the counter 1105 becomes an upper data of the digital data. Thus, the digital data corresponding to the level of the analog signal is obtained.
Hereinafter, the case in which the signal (the lower phase signal) held by the latch unit 1108 is a 16-bit data signal and the count value (the upper count value) held by the counter 1105 is an 8-bit data signal will be described.
For encoding of the lower phase signal, it is preferable to perform a comparison of a multiple value (detecting whether the logic states of consecutive n numbers, for example, two lower phase signals are in a predetermined state) used for a flash type ADC in time series, while changing the lower phase signal which is a comparison target. In detail, a method of detecting whether the logic states of the two lower phase signals are in a predetermined logic state, for example, “01” (L state and H state) is performed in time series. The encode method is applied to the TDC type AD conversion circuit using the asymmetric type oscillation circuit illustrated in FIG. 11.
The states (a combination of the logic states of each of the lower phase signals CK[0] to CK[15]) of the lower phase signals CK[0] to CK[15] latched by the latch unit 1108 become a total of 16 states, for example, state 0 to state 15 as illustrated in FIG. 10. When the counter 1105 counts at the rising edge of the lower phase signal CK[13], the combination of the logic states of the lower phase signals CK[0] to CK[15] in each period equally divided into sixteen from a period (a period from the rising edge of the lower phase signal CK[13] to the next rising edge) counted by one by the counter 1105 becomes state 0 to state 15. State 0 to state 15 correspond to encode values 0 to 15 which are the encode results.
Hereinafter, a process of detecting whether the logic states of the two lower phase signals are in a predetermined logic state (in the present example, “01”) will be described. FIG. 11 illustrates waveforms of the start pulse StartP and the output signal (lower phase signals CK[0] to CK[15]) of the VCO 1100. In FIG. 11, the lower phase signals CK[0] to CK[15] illustrated in FIG. 10 are arranged so as to be a signal group which rises (changed from an L state to an H state) in order at a predetermined time interval. In detail, each lower phase signal is arranged in order of the lower phase signals CK[15], CK[0], CK[2], CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], and CK[13].
As illustrated in FIG. 11, when the lower phase signal CK[15] is changed from an L state to an H state and then a predetermined time (corresponding to a delay time of the two NAND circuits) lapses, the lower phase signal CK[0] is changed from an L state to an H state. When the lower phase signal CK[0] is changed from an L state to an H state and then the predetermined time (corresponding to the delay time of the two NAND circuits) lapses, the lower phase signal CK[2] is changed from an L state to an H state.
After that, similarly, the lower phase signals CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], and CK[13] are changed from an L state to an H state in series.
During the encoding of the lower phase signal, in a signal group (a signal sequence) in which the lower phase signals CK[15], CK[0], CK[2], CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], and CK[13] latched by the latch unit 1108 are arranged in this order, the case in which the logic states of the two consecutive lower phase signals become an L state and an H state in order respectively is detected and encode values are determined depending on a position at which the logic states are detected.
FIG. 12 illustrates a correspondence relationship between the logic states of the lower phase signals latched by the latch unit 1108 and the encode values corresponding to the logic states of the lower phase signals. In FIG. 12, each lower phase signal is arranged so that the order thereof becomes the same as the order of each lower phase signal in FIG. 11. In detail, the order of each lower phase signal as seen from the top to the bottom in order in FIG. 11 is the same as the order of each lower phase signal as seen from the right to the left in order in FIG. 12.
In FIG. 12, “1,” “0,” and “1/0” represent the logic states of each lower phase signal. “1,” “0,” and “1/0” correspond to an “H state,” an “L state,” and an “H state or L state,” respectively. The logic states of the lower phase signals input to the latch unit 1108 are changed in time series and the encode values corresponding to the timing latched by the latch unit 1108 are obtained.
In FIG. 12, the encode values are determined corresponding to a combination of the signals in which the logic states of the two consecutive lower phase signals become “0” and “1” in order respectively. For example, when the logic states of the lower phase signals CK[15] and CK[13] are “0” and “1” respectively, the encode value is “0” and when the logic states of the lower phase signals CK[0] and CK[15] are “0” and “1” respectively, the encode value is “1”. Similarly, when the logic states of the lower phase signals CK[13] and CK[11] are “0” and “1” respectively, the encode value is “15.”
In the above description, the lower phase signal CK[13] is a count clock of the counter 1105, but the present invention is not limited thereto and therefore any lower phase signal may be used as the count clock of the counter 1105. For example, when the lower phase signal CK[2] becomes the count clock of the counter 1105, a process of detecting whether the logic states of the two lower phase signals is a predetermined state (in the present example, “01”) is as follows.
The states (the combination of the logic states of each of the lower phase signals CK[0] to CK[15]) of the lower phase signals CK[0] to CK[15] latched by the latch unit 1108 become a total of 16 states, for example, state 0 to state 15 as illustrated in FIG. 13. When the counter 1105 counts at the rising edge of the lower phase signal CK[2], the combination of the logic states of the lower phase signals CK[0] to CK[15] in each period equally divided into sixteen from a period (a period from the rising edge of the lower phase signal CK[2] to the next rising edge) counted by one by the counter 1105 becomes state 0 to state 15. State 0 to state 15 correspond to the encode values 0 to 15 which are the encode results.
FIG. 14 illustrates waveforms of the start pulse StartP and the output signal (lower phase signals CK[0] to CK[15]) of the VCO 1100. In FIG. 14, the lower phase signals CK[0] to CK[15] illustrated in FIG. 13 are arranged so as to be a signal group which rises (changed from an L state to an H state) in order at a predetermined time interval. In detail, each lower phase signal is arranged in order of the lower phase signals CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13], CK[15], CK[0], and CK[2].
As illustrated in FIG. 14, when the lower phase signal CK[4] is changed from an L state to an H state and then the predetermined time (corresponding to the delay time of the two NAND circuits) lapses, the lower phase signal CK[6] is changed from an L state to an H state. When the lower phase signal CK[6] is changed from an L state to an H state and then the predetermined time (corresponding to the delay time of the two NAND circuits) lapses, the lower phase signal CK[8] is changed from an L state to an H state.
After that, similarly, the lower phase signals CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13], CK[15], CK[0], and CK[2] are changed from an L state to an H state in series.
During the encoding of the lower phase signals, in a signal group (a signal sequence) in which the lower phase signals CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13], CK[15], CK[0], and CK[2] latched by the latch unit 1108 are arranged in this order, the case in which the logic states of the two consecutive lower phase signals become an L state and an H state in order respectively is detected and the encode values are determined depending on a position at which the logic states are detected.
FIG. 15 illustrates a correspondence relationship between the logic states of the lower phase signals latched by the latch unit 1108 and the encode values corresponding to the logic states of the lower phase signals. In FIG. 15, each lower phase signal is arranged so that the order thereof becomes the same as the order of each lower phase signal in FIG. 14. In detail, the order of each lower phase signal as seen from the top to the bottom in order in FIG. 14 is the same as the order of each lower phase signal as seen from the right to the left in order in FIG. 15.
In FIG. 15, “1,” “0,” and “1/0” represent the logic states of each lower phase signal. “1,” “0,” and “1/0” correspond to an “H state,” an “L state,” and an “H state or L state,” respectively. The logic states of the lower phase signals input to the latch unit 1108 are changed in time series and the encode values corresponding to the timing latched by the latch unit 1108 are obtained.
In FIG. 15, the encode values are determined corresponding to the combination of the signals in which the logic states of the two consecutive lower phase signals become “0” and “1” in order respectively. For example, when the logic states of the lower phase signals CK[4] and CK[2] are “0” and “1” respectively, the encode value is “0” and when the logic states of the lower phase signals CK[6] and CK[4] are “0” and “1” respectively, the encode value is “1.” Similarly, when the logic states of the lower phase signals CK[2] and CK[0] are “0” and “1” respectively, the encode value is “15.”
In the TDC type AD conversion circuit including the asymmetric type oscillation circuit, like the lower phase signal CK[0] and the lower phase signal CK[15], a plurality of signals which substantially simultaneously falls (or rises) are present in principle.
Therefore, as will be described later, errors in lower data which are obtained by the encoding may occur.
Hereinafter, the case in which the lower phase signal CK[13] becomes the count clock of the counter 1105 will be described by way of example. As illustrated in FIG. 16, the logic states of the lower phase signals CK[0] and CK[15] may become “0” and “1” respectively in the case in which large noises overlap in a buffer etc. which transmits the lower phase signal CK[0] or the lower phase signal CK[15], thus the lower phase signals CK[0] to CK[15] are latched by the latch unit 1108 at the timing at which the phase of the lower phase signal CK[0] is advanced from the phase of the lower phase signal CK[15] and the like.
When the logic states of the lower phase signals CK[0] to CK[15] latched by the latch unit 1108 become as illustrated in FIG. 16, if encoded by using an encoding method of determining encode values depending on a position at which the logic states of the two consecutive lower phase signals become “0” and “1” in order respectively, the logic states of the lower phase signals CK[1] and CK[14] are detected as “0” and “1” and the logic states of the lower phase signals CK[0] and CK[15] are detected as “0” and “1.” As such, if there are two positions at which the logic states of the two consecutive lower phase signals are in a predetermined logic state, the encode value is supposed to be “9” originally. However, the encode value may be “1.” In this case, an error of “8” which is a difference between “9” and “1” occurs in the lower data.
Alternatively, even when the lower phase signal CK[2] becomes the count clock of the count unit 1105, in the case in which the lower phase signals CK[0] to CK[15] are latched by the latch unit 1108 at the timing at which the phase of the lower phase signal CK[0] is advanced from the phase of the lower phase signals CK[15] and the like, as illustrated in FIG. 17, the logic states of the lower phase signals CK[0] and CK[15] may be “0” and “1” respectively.
When the logic states of the lower phase signals CK[0] to CK[15] latched by the latch unit 1108 are as illustrated in FIG. 17, if encoded by using an encoding method of determining encode values depending on a position at which the logic states of the two consecutive lower phase signals are “0” and “1” in order respectively, the logic states of the lower phase signals CK[1] and CK[14] are detected as “0” and “1” and the logic states of the lower phase signals CK[0] and CK[15] are detected as “0” and “1.” As such, if there are two positions at which the logic states of the two consecutive lower phase signals are in a predetermined logic state, the encode value is supposed to be “6” originally. However, the encode value may be “14. In this case, an error of “8” which is a difference between “6” and “14” occurs in the lower data.